초록 열기/닫기 버튼
In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage (Vamb) and double gate structure is applied to improve on-current (ION) and subthreshold swing (SS). We discussed the fin width (WS), body doping concentration, sidewall width (Wside), drain and gate underlap distance (Xd), source doping distance (XS) and pocket doping length (XP) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high ION of 1.2 10-3 A/ m and low Vamb of -2.0 V.
